Among nonvolatile memories, an MRAM (Magnetoresistive Random Access Memory) and an SPRAM (Spin Transfer Torque RAM) which are memories utilizing magnetoresistance change are capable of a high-speed operation, and have a possibility of forming a nonvolatile RAM that can be rewritten a practically unlimited number of times. As shown in a circuit diagram of FIG. 21A, the cell of the SPRAM described in Non-Patent Document 1 and Non-Patent Document 2 is constituted by one tunnel magnetoresistive element TMR, a selection transistor MCT, a word line WL, a bit lie BL, and a source line SL. FIG. 21B shows an example of a cross-sectional structure thereof. As shown in FIG. 22, the tunnel magnetoresistive element TMR has at least two magnetic layers, and one of them is a pinned layer PL in which a spin direction is fixed and the other is a free layer FL in which the spin direction takes two states relative to the pinned layer, that is, a parallel state and an anti-parallel state. A tunnel barrier film TB is disposed between these films. The information storage is achieved based on the spin directions in this free layer, and in the case of the anti-parallel state (AP) relative to the pinned layer of FIG. 22A, the electric resistance of the tunnel magnetoresistive element becomes a high resistance state, while in the case of the parallel state (P) of FIG. 22B, it becomes a low resistance state. These states are assigned to “0” and “1” of the information. In a reading operation, the magnitude of the resistance of the tunnel magnetoresistive element TMR is read to obtain the stored information. In a rewriting operation, the spin direction of the free layer can be controlled by an electric current in a direction perpendicular to the pinned layer PL, the tunnel barrier film TB, and the free layer FL. More specifically, when an electric current is applied in a direction from the pinned layer PL to the free layer FL, electrons having a spin direction that makes the direction of magnetization of the free layer reverse to that of the pinned layer PL mainly flow toward the free layer FL. For this reason, when this current value exceeds a predetermined threshold value, the directions of magnetization of the pinned layer PL and the free layer FL become anti-parallel to each other. In contrast, when an electric current is applied in a direction from the free layer FL to the pinned layer PL, electrons having a spin direction that makes the direction of magnetization of the free layer equal to that of the pinned layer PL mainly flow toward the free layer FL. When this current value exceeds a predetermined threshold value, the directions of magnetization of the pinned layer PL and the free layer FL become parallel to each other. More specifically, in this memory, the information “0” and the information “1” are written separately based on the directions of the electric current. In the case when this system is used, since the electric current (threshold value) required for rewriting is proportional to the size of the tunnel magnetoresistive element TMR, miniaturization and reduction in the rewriting current can be achieved, so that this method is superior in scalability. For the tunnel barrier film TB, a material such as MgO can be used.
As described in Non-Patent Documents 1 and 2, the feature of this memory is that information is not lost even when a power supply is shut off, that is, the memory is nonvolatile. Moreover, in comparison with the flash memory, this memory has an extremely large number of rewritable times, and can be continuously rewritten unlimitedly for 10 years. In other words, it can be used in the same manner as the DRAM and SRAM. Moreover, like the DRAM and SRAM, this memory can carry out reading and writing operations of “1” information and “0” information at random places in the same period of time. The flash memory does not have these functions, and even a memory cell that stores binary numbers carries out divided operations, that is, an operation referred to as an erasing operation in which memory cells in a certain region are entirely brought into, for example, a memory state of “0” and an operation referred to as a writing operation in which specified memory cells among these memory cells in an erased state are brought into a memory state of “1”. These asymmetric operations are not required in the MRAM and SPRAM. Although this memory is capable of carrying out the same operations as those of the SRAM and DRAM, it is also nonvolatile like the flash memory. Therefore, it is not necessary to selectively use the volatile SRAM and DRAM and the nonvolatile flash memory unlike the conventional case, and it becomes possible to reduce the number of parts and also to make the hierarchical levels of the memory control shallower.